PCIe testing usually requires advanced check techniques and engineers with deep experience and information. Furthermore, it takes hours and even days of setup and testing, usually stretching prices to seven figures. A brand new check answer claims to interrupt the conventions of PCIe testing by delivering check leads to minutes whereas providing a mixture of plug-and-play setup and easy-to-use interface.
TMT4 Margin Tester—a specialised testing instrument for the design and validation of PCIe Gen 3 and Gen 4 motherboards, add-in playing cards, and system designs—allows engineers in any respect ranges of expertise to judge the well being of transmitter (Tx) and receiver (Rx) hyperlinks sooner than ever. It helps the vast majority of widespread PCIe kind components—together with CEM, M.2, U.2, and U.3—with testing capabilities of as much as 16 lanes throughout PCIe presets 0-9 whereas utilizing a single customary connector.
Full Tx/Rx protocol functionality allows hyperlink well being analysis of PCIe Gen 3 and Gen 4 communications on either side of the hyperlink in a single field. Supply: Tektronix
Tektronix’s TMT4 Margin Tester is constructed on the Intel Stratix 10 FPGA with PCIe. Rina Raman, VP and GM of DCAI for Embedded Acceleration Division at Intel, acknowledges that the outcomes can be found considerably sooner, usually, in minutes fairly than hours. Raman additionally pointed to TMT4’s capability to establish design points a lot earlier within the design course of.
Take a look at engineers can conduct the sooner and extra frequent evaluations of board- or system-level hyperlink well being throughout design and validation. In accordance with Chris Witt, VP and GM of Portfolio Options at Tektronix, the TMT4 tester is meant to enhance full validation and compliance testing techniques consisting of oscilloscopes and BERTs. “It could actually uncover points earlier within the design course of earlier than an in-depth examination utilizing conventional gear.”
TMT4’s simplified setup and configuration goal to attenuate the necessity for senior-level engineers to carry out hyperlink well being evaluations. Subsequent, its multi-lane testing capabilities allow customers to considerably enhance total testing occasions by lowering the variety of connection adjustments wanted to carry out testing.
In TMT4 Margin Tester, Fast Scan mode allows analysis of hyperlink well being for Gen 3 or Gen 4 units for as much as 16 lanes. Then there may be Customized Scan mode that gives deeper insights by permitting customers to scan Gen 3 or 4 units for as much as 16 lanes throughout PCIe presets 0-9 with as much as 160 combos in as little as 20 minutes.
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