Mitigating kernel dangers on 32-bit ARM

Sarcastically, at these low value factors, the DRAM is definitely the dominant element when it comes to BOM value, and lots of of those 32-bit ARM techniques incorporate an affordable ARMv8 SoC that occurs to be able to operating in 64-bit mode as properly. The explanation for operating 32-bit functions nonetheless is that these typically use much less of the costly DRAM, and might be deployed straight with out the necessity to recompile the binaries. As 32-bit functions do not want a 64-bit kernel (which itself makes use of extra reminiscence as a consequence of its inner use of 64-bit pointers), the product ships with a 32-bit kernel as an alternative.

In case you’re selecting to make use of a 32-bit kernel for its smaller reminiscence footprint, it is not with out dangers. You may seemingly expertise efficiency points, unpatched vulnerabilities, and surprising misbehaviors reminiscent of:

• 32-bit kernels typically can not handle greater than 1 GiB of bodily reminiscence with out resorting to HIGHMEM bouncing, and can’t present a full digital deal with area of 4 GiB to consumer area, as 64-bit kernels can.
• Aspect channels or different flaws brought on by silicon errata might exist that have not been mitigated in 32-bit kernels. For instance, the hardening towards Spectre and Meltdown vulnerabilities had been solely achieved for ARMv7 32-bit solely CPUs, and lots of ARMv8 cores operating in 32-bit mode should still be susceptible (solely Cortex-A73 and A75 are dealt with particularly). And on the whole, silicon flaws in 64-bit elements that have an effect on the 32-bit kernel are much less more likely to be discovered or documented, just because the silicon validation groups don’t prioritize them.
• The 32-bit ARM kernel doesn’t implement the flowery alternate options patching framework that’s utilized by different architectures to implement dealing with of silicon errata, that are specific to sure revisions of sure CPUs. As an alternative, on 32-bit multiplatform kernels, we merely allow all errata workarounds that could be wanted by any of the cores which will ever run the picture in query, doubtlessly affecting efficiency unnecessarily on cores that don’t have any want for them.
• Silicon distributors are phasing out 32-bit help in the long run. Given an ecosystem containing a handful of working techniques and 1000’s of functions, help for 32-bit working techniques (which is extra advanced technically) is extremely more likely to be dropped first. For merchandise with longer life cycles, long-term procurement contracts for parts accessible right now are normally way more pricey than adjusting the BOM over time and utilizing newer, cheaper elements.
• The 32-bit kernel doesn’t implement kernel deal with area randomization, and even when it did, its comparatively tiny deal with area merely leaves little or no area for randomization. Different hardening options, reminiscent of rodata=full or hierarchical eXecute By no means attributes, are lacking as properly on 32-bit, and will not be more likely to be applied, both as a consequence of lack of help within the structure, or due to the complexity of the 32-bit reminiscence administration code, which nonetheless helps the entire completely different structure revisions relationship again to the preliminary Linux port operating on the Risc PC.

Conserving the 32-bit ARM kernel safe

There are instances, although, the place utilizing the 32-bit kernel is the one possibility, e.g., if the CPUs are in actual fact 32-bit solely (which is the case even for some ARMv8 cores reminiscent of Cortex-A32), or when counting on an present 32-bit solely codebase operating within the kernel (drivers for legacy peripherals). Word that in such instances, it nonetheless is sensible to make use of the newest kernel model suitable with the {hardware}, since we’re in actual fact making an effort to allow a number of the present hardening options on 32-bit ARM as properly.

• THREAD_INFO_IN_TASK for v7 SMP cores

The v5.16 launch of the Linux kernel implements help for THREAD_INFO_IN_TASK when operating on ARMv7 SMP techniques. This protects the kernel’s per-task bookkeeping (known as thread_info), which lives on the far (and usually unused) finish of the stack, towards stack overflows which can happen in uncommon -yet generally exploitable- instances the place the management circulate of this system merely finally ends up accumulating extra state than the stack can maintain. (Word {that a} stack overflow is just not the identical as a stack buffer overflow, the place the overflow occurs in the wrong way.)

By shifting thread_info off the stack and into the kernel heap, and through the use of a particular SMP CPU register to maintain observe of its location, we are able to mitigate the danger of stack overflows leading to thread_info corruption. Nevertheless, it doesn’t forestall stack overflows themselves: these should still happen, and lead to corruption of different knowledge constructions that occur to be adjoining to the duty stack in reminiscence.

• THREAD_INFO_IN_TASK for different cores

For CPUs that lack this particular SMP CPU register, we additionally proposed an implementation of THREAD_INFO_IN_TASK that’s anticipated to land in v5.18. As an alternative of a particular register, it makes use of a worldwide variable to maintain observe of the placement of thread_info.

Stopping stack overflows from corrupting unrelated reminiscence contents is the aim of VMAP_STACK, which we’re enabling for 32-bit ARM as properly. When VMAP_STACK is enabled, kernel mode stacks are allotted from the kernel heap as earlier than, however mapped into a unique a part of the kernel’s deal with area, and surrounded by guard areas, that are assured to be saved unpopulated. Provided that accesses to such unpopulated areas will set off an exception, the kernel’s reminiscence administration layer can step in and terminate this system as quickly as a stack overflow happens, and stop it from inflicting reminiscence corruption.

Help for IRQ stacks

Arising with a bounded worst case on which to base the scale of the kernel stack is fairly laborious, particularly given the truth that it’s shared between this system itself and any exception dealing with routines that could be known as on its behalf, together with interrupt handlers. To mitigate the danger of a pathological worst case occurring, the place an interrupt fires that wants quite a lot of stack area proper at a time when many of the stack is already being utilized by this system, we’re additionally enabling IRQ_STACKS for 32-bit ARM, which can run handlers of each laborious and tender interrupts from a devoted stack, one for every CPU. By decoupling the duty and interrupt contexts like this, the chance {that a} well-behaved program must be terminated as a consequence of stack overflow ought to be all however eradicated.

Conclusion

With these modifications in place, kernel stack overflow safety can be accessible for all ARM techniques supported by Linux, together with historic ones just like the Risc PC or Netwinder, supplied that it runs a Linux distribution that’s maintaining with the occasions.

Nevertheless, counting on legacy {hardware} and software program comes with a danger, and despite the fact that we attempt to assist maintain customers of the 32-bit kernel as secure as we fairly can, it’s not the proper selection for brand spanking new designs that incorporate 64-bit succesful {hardware}.