Sunday, September 18, 2022
HomeElectronicsJOB: DDR Lead Verification Engineer at Cadence

JOB: DDR Lead Verification Engineer at Cadence


Location: Bengaluru and Pune

Firm: Cadence

Place Description:

  • Practical Verification Engineer for DDR Reminiscence Controller and PHY IP growth crew.
  • The place is predicated in Bangalore.
  • The function would come with purposeful verification of the DDR Reminiscence Controller and PHY IP answer of Cadence.
  • The work concerned will probably be working with the present purposeful verification atmosphere, the addition of latest options into the verification atmosphere, guaranteeing varied buyer configurations are clear as a part of verification regressions, supporting prospects in case of any points with utilizing the verification atmosphere, and purposeful and code protection.
  • The engineer could be accountable to make sure that the design is in keeping with the technical and high quality necessities set for the crew – significantly with respect to purposeful and code protection.

Place Necessities:

    • BE/BTech/ME/MTech – Electrical / Electronics / VLSI with expertise as a design and verification engineer, with a big portion of the current work expertise on verification atmosphere growth.
    • Robust background in purposeful verification fundamentals, atmosphere planning, take a look at plan technology, and atmosphere growth is a should.
    • System Verilog expertise and expertise with UVM-based purposeful verification atmosphere growth are required.
    • Prior RTL Design expertise utilizing Verilog is a should – in order that the verification engineer is self-sufficient for many features of debugging.
    • The Newest DDR Protocol expertise is extremely fascinating. Prior expertise in purposeful verification and debugging of advanced protocols is a should.
    • AXI3/4 expertise is fascinating.
    • Prior expertise in IP growth groups could be an added benefit.



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