Indian Institute of Science (IISc) researchers have developed a design framework to construct next-generation analog computing chipsets. Utilizing this design framework, they’ve constructed a prototype of an analog chipset referred to as ARYABHAT-1 (Analog Reconfigurable technologY And Bias-scalable {Hardware} for AI Duties). IISc mentioned that this sort of chipset might be very useful for AI-based functions reminiscent of object or speech recognition and those who require large parallel computing operations at excessive speeds..
The researchers have outlined their findings in two pre-print research (presently beneath peer evaluate). They’ve additionally filed patents and intend to work with trade companions to commercialise the know-how.
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Picture: IISc
Most digital gadgets use digital chips as a result of the design course of is straightforward and scalable. Chetan Singh Thakur, Assistant Professor on the Division of Digital Techniques Engineering (DESE), IISc, mentioned that the benefit of utilizing analog is huge, particularly by way of energy utilization and measurement.
IISc states some difficulties related to analog processors:
- Testing and co-design analog processors are troublesome.
- Analog chips don’t scale simply. So, they must be individually customised whereas transitioning to the subsequent technology know-how or to a brand new software. This makes their design costly.
- The trade-off between precision and pace with energy and space shouldn’t be straightforward with regards to analog design.
The researchers mentioned that completely different machine studying architectures may be programmed on ARYABHAT and may function robustly throughout a variety of temperatures. The structure can be “bias-scalable.” Its efficiency stays the identical when the situations like voltage or present are modified.
