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International Unichip Corp. (GUC), the Superior ASIC Chief, has introduced that GLink 2.3LL (GUC’s die-to-die Hyperlink) interface IP for TSMC CoWoS® and InFO chiplets integration platforms handed silicon validation and might be showcased on the TSMC 2022 Open Innovation Platform® (OIP) Ecosystem Discussion board in Santa Clara Conference Heart on Oct 26, 2022.
Die edge is the scarcest useful resource and GLink 2.3LL permits essentially the most environment friendly use of it by transferring 2.5 Tbps of full duplex person site visitors per each mm of die edge. With end-to-end latency of 5 ns and measured energy consumption of 0.27 pJ/bit, that is essentially the most environment friendly chiplet interface available on the market. GLink 2.3LL helps InFO_oS and all CoWoS sorts (each silicon –S and natural interposers -R). Main AI, CPU and Automotive clients have adopted it for his or her subsequent technology merchandise.
GUC offers full AXI, CXS or CHI bus bridges with configurable parameters (bus width and different properties) utilizing a GLink 2.3LL bodily interface. Built-in TX and RX Clock Area Crossing (CDC) FIFOs enable impartial clock frequencies for interconnecting dies, which may be modified on the fly with none knowledge site visitors interruption. The GLink 2.3LL IP features a Hyperlink Coaching {hardware} state machine and computerized monitoring of voltage-temperature adjustments throughout regular operation, in order that the person software program just isn’t concerned in interface management. The coaching and monitoring are accomplished solely on the RX facet with none die-to-die interplay, assembly strict Automotive Practical Security necessities. The GLink 2.3LL I/Os’ excessive cross-talk tolerance permits CoWoS/InFO unshielded routing, successfully doubling the variety of sign traces for the interposer or RDL. GLink 2.3LL has redundant lanes that change defective ones throughout manufacturing assessments or within the subject. The proteanTecs interconnect monitoring system is built-in within the PHY. It may be used to watch the sign high quality of each bodily lane throughout regular operation so as to observe lane degradation because of TSMC CoWoS or InFO_oS bodily results. This helps selections to interchange marginal high quality lanes with redundant ones to stop system failures and prolong the product’s life cycle.
The model of GLink 2.3LL for TSMC N3E might be accessible in Q1, 2023 and the GLink automotive model on TSMC N5A course of might be prepared in 2024. GUC’s implementation of UCIeTM takes benefit of our experience with many silicon-proven generations of GLink IPs, making our path to UCIeTM low danger.
“Chiplet-based architectures utilizing CoWoS and InFO have grow to be mainstream for infrastructure merchandise and GUC is uniquely positioned with its lengthy expertise of growing HBM and GLink IPs and high-volume manufacturing CoWoS merchandise. With the brand new GLink 2.3LL silicon validation, GUC demonstrates its long-term dedication to offering essentially the most aggressive 2.5D whole resolution, together with a first-in-the-industry silicon-proven HBM3 PHY & Controller, GLink 2.5D and 3D chiplet interfaces, electrical and thermal simulations, package deal design, DFT and manufacturing assessments, CoWoS and InFO manufacturing experience,” explains Sean Tai, president of GUC.
“We’re designing our IPs for error-free operation in >1000W multi-chiplet ASICs. We check their immunity to excessive energy noise, temperature and voltage biking, with months of error-free operation in very harsh circumstances. We leverage our ASIC manufacturing expertise to outline a complete silicon validation check suite. We’re dedicated to doubling bandwidth density yearly whereas protecting energy and latency low, enabling the CPU, GPU, DPU, AI, Automotive and Community Processors of the long run,” mentioned Igor Elkanovich, CTO of GUC.
Key GLInk 2.3LL Highlights
- Course of: TSMC N5/N4, N3E and N5A (automotive)
- 2.5 Tbps full duplex person site visitors per 1 mm of beachfront
- Measure energy: 0.27pJ/bit (i.e., 0.27W per 1 Tbps of full duplex person site visitors, TX and RX concurrently)
- AXI, CXS and CHI die-to-die bredges with 5 ns bus-to-bus latency, together with TX and RX clock area crossing (CDC) FIFOs
- Suport inFO-oS and all CoWoS-S/R/L sorts (each silicon and natural interposers)
- Uncooked BER < 1E-20 and BER << 1FIT after built-in CRC error checks and retransmission utilizing built-in replay buffer
Be taught Extra about GUC’s GLink IP with InFO/CoWoS Whole Answer
For extra info, please contact your GUC gross sales consultant instantly or e mail guc_sales@guc-asic.com
About GUC
GLOBAL UNICHIP CORP. (GUC) is the Superior ASIC Chief, who offers the semiconductor {industry} with main IC implementation and SoC manufacturing companies, utilizing superior course of and packaging expertise. Primarily based in Hsin-chu Taiwan, GUC has developed a world repute with a presence in China, Europe, Japan, Korea, and North America. GUC is publicly traded on the Taiwan Inventory Change below the image 3443. For extra info, go to www.guc-asic.com
