TSMC has licensed the Cadence digital and customized/analog design flows for its N4P and N3E course of applied sciences. These design flows assist TSMC’s newest Design Rule Guide (DRM) and FINFLEX know-how. By continued collaborations, the 2 firms have delivered the corresponding N4P and N3E course of design kits (PDKs) to speed up advanced-node cellular, automotive, AI, and hyperscale computing improvement.
Cadence’s TSMC-certified RTL-to-GDS digital circulate consists of the Innovus Implementation System, Quantus Extraction Resolution, Quantus FS resolution, Tempus Timing Signoff Resolution and ECO choice, Pegasus Verification System, Liberate Characterization Resolution, Voltus IC Energy Integrity Resolution, and Voltus-Fi Customized Energy Integrity Resolution. The Genus Synthesis Resolution and predictive iSpatial know-how are additionally enabled for the TSMC N4P and N3E processes.
Each the Virtuoso Design Platform and the Spectre Simulation Platform analog design flows, in addition to the customized design reference circulate (CDRF), have been enhanced to assist the TSMC N4P and N3E processes. The Virtuoso Design Platform offers a good integration with the Innovus Implementation System, which augments the implementation methodology of mixed-signal designs through a typical database.
Study extra about Cadence’s digital and customized/analog advanced-node options right here.
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