An inside laptop aided design (CAD) or design providers engineer is answerable for delivering environment friendly, sturdy and high-quality design movement options. The design movement on a day-to-day foundation retains chip designers and verification engineers productive and targeted on their jobs, stopping them from debugging CAD instruments and flows and creating advert hoc and undocumented scripts. Over the lifetime of a venture, a high-quality design movement differentiates an organization from rivals and might be the distinction between getting chips to market first or being the sufferer of surprising course of bottleneck and delays.
And but, each semiconductor venture group offers with inefficiencies that constrain them from delivering supreme options and limits productiveness. Right this moment’s CAD engineers use a patchwork of instruments, flows and scripts consisting of economic digital design automation (EDA) merchandise, industrial or in-house personalized add-ons and in-house mental property (IP), an issue for a lot of venture teams due to:
- Instrument movement gaps in present EDA merchandise
- The burden of sustaining in-house or homegrown instruments, flows and scripts
- The shortage of time to construct and take a look at high-quality, sturdy inside instruments
That inevitably results in a bunch of issues, as defined within the following sections.
Limitless script design loops
The burden of sustaining in-house or homegrown instruments, flows and scripts is considered one of cascading interventions. It could begin out with a design engineer writing a Perl or Tcl script to beat a roadblock within the design verification course of.
Because the venture group makes use of it, particular instances and features don’t work. The script will get one other rework to refine it and will get handed as much as the chip lead for assessment who notes enhanced automation, then notices that the script doesn’t deal with one thing essential.
Extra points come up as extra of the venture group makes use of the script. The script will get handed to the inner CAD group for ongoing help and upkeep. Extra points come up as the inner CAD division begins to make use of it. CAD spends three weeks engaged on the script to handle these points and ongoing upkeep requires at some point per week.
It’s not lengthy earlier than help and upkeep of 1 inside script prices between $50,000 and $100,000 per 12 months. In the long run, the script was required for the event course of, however the monetary and venture time price is excessive and unpredictable.
The burden of upkeep contains guaranteeing present inside instruments and flows proceed to work. Different upkeep choirs could possibly be including options to present inside instruments and flows, and shifting to a brand new {hardware} description language (HDL), reminiscent of Verilog to SystemVerilog, or including help for a further HDL attributable to third-party IP. The estimated price of updating only one in-house Perl or Tcl script to help SystemVerilog might be $175,000 and 6 months of venture time.
Time is the enemy
An organization’s main objective is to get the silicon system to market quick. The CAD division’s job is to help the designers and verification engineers, which suggests persevering with to prop up the patchwork of instruments, flows and scripts hybridized from industrial EDA merchandise and in-house IP.
The shortage of time to construct sturdy instruments is an issue. A CAD engineer is aware of what she or he desires a software to do, is aware of how you can design, implement and take a look at it, however doesn’t have the time to do it.
Homegrown fixes embrace:
- Turning to open-source parser initiatives, although they by no means have the total language protection or help for brand new constructs.
- Rewriting inside flows and scripts and utilizing extra sturdy software program engineering methodologies, a tough job to justify the sources to “re-do” work.
- Switching from Perl or Tcl to Python for higher understandability and performance. This doesn’t resolve HDL complexity—the SystemVerilog language reference handbook (LRM) is 1,300 pages of complicated specs.
- Jury-rigging present industrial EDA instruments to carry out duties they weren’t meant to do usually finally ends up with unsatisfactory outcomes and a dependency on costly licenses.
On the similar time, the venture group is taking an enormous danger if CAD is unable to persistently ship best-in-class design and verification flows. Lacking market home windows and/or delivering silicon that isn’t aggressive might be deadly to a semiconductor firm given the brand new product cycles and excessive prices of IC improvement.
Options exist and vary from in-house improvement of {custom} instruments to buying a personalized software constructed by an EDA firm, with variations in between.
4 methods to construct best-in-class CAD flows
One
Creating sturdy, high-performance CAD instruments in-house would yield a license-free, proprietary software that could possibly be the key weapon to reliably get a chip to market first. It will require constructing a parser from scratch to detach from any licensing agreements.
Disadvantages are:
- It may be extraordinarily time consuming.
- It requires a deep understanding of HDL languages and the way they’re used.
- Outcomes will not be sturdy as a result of the underlying infrastructure is weak and untested.
- The software might have insufficient testing, resulting in an iterative help mannequin.
- It could not monitor new developments in HDL languages.
- Deployment time could possibly be lengthy, starting from one 12 months to a number of years.
Two
License a C++ parser library and rent a software program improvement group to construct {custom} CAD instruments that bypass present limitations. This answer is an outsourced variation of the earlier one. Commercially out there parsers provide advantages, together with full-language protection for VHDL, Verilog, SystemVerilog and UPF.
Inner CAD teams are sometimes extra skilled in scripting model languages reminiscent of Perl, Tcl and Python and will not have the depth of improvement experience in C++. The C++ library might be tough to make use of with out in depth C++ software program improvement experience.
Three
Ask an EDA vendor to {custom} construct options/perform wanted to allow a design movement. A bonus of this answer can be help and upkeep of the requested functionality if it’s built-in into the mainline of the product. A consulting venture by the EDA vendor would imply the accountability for extra ongoing consulting providers to take care of the function/perform.
What’s extra, the corporate can be beholden to the EDA vendor’s schedule or the seller might not construct or have the ability to construct the customization. The EDA vendor might require upfront cost for non-recoverable engineering (NRE) prices and, if the EDA vendor provides requests to its subsequent launch, a personalized function or perform turns into out there to rivals. Moreover, if the EDA vendor builds a personalized software, there might be ongoing obligations for IP points and licensing necessities.
As well as, relying on the character of the venture and engagement, the EDA vendor might present the requested performance to its different clients, thereby dropping any aggressive benefit related to the options/perform. Many EDA distributors additionally present utility engineering help for customizing their software integration into their clients’ flows. As a result of this sort of experience is often supplied to different main licensees, it’s not prone to impart a aggressive benefit.
4
License a CAD software improvement platform that incorporates built-in HDL parsers, industrial-quality databases and help for traditional file codecs for in-house improvement utilizing mainstream scripting environments. A platform answer like that is supposed for design, verification and CAD engineers to rapidly create focused {custom} functions for semiconductor design and verification.
A sturdy, high-performing and easy-to-use CAD software improvement platform ought to:
- Present full parsing of Verilog, SystemVerilog, Verilog-AMS, VHDL, Liberty and UPF.
- An intuitive API with a language acquainted to a {hardware} engineer reminiscent of Python that abstracts complexity and permits particular management when wanted.
- Be pre-tested on a big set of benchmarks that show typical use instances and the entire HDL language behaviors, together with constructs and use instances.
- A help mannequin that describes utilizing the software and entry to consulting providers to complement improvement.
- Absolutely operational pattern functions simply modified for a consumer’s particular case.
CAD software improvement platform
The most important problem that inside teams face is getting access to sturdy, easy-to-use and keep and regularly supported HDL parsing environments. A CAD software improvement platform offering each ease of use and sturdy capabilities would free the group from the boundaries of economic EDA flows whereas providing capabilities to distinguish its design movement. Further advantages are price financial savings on EDA software licenses, time financial savings in CAD instruments, movement and script improvement and elevated productiveness for design, verification and CAD engineers.
The CAD software improvement platform would require an upfront funding, somewhat than making use of free scripting instruments like Perl and Tcl, a disadvantage that must be thought of. With the transfer from Verilog to SystemVerilog, for instance, easy Perl or Tcl scripts usually are not possible as a result of extra complexities of the language. A CAD software improvement platform designed for HDL exploration and modification will allow new and modern instruments and flows not potential utilizing general-purpose text-parsing capabilities.
A CAD software improvement platform is an funding that enables totally utilized human capital; beneficial R&D sources fascinated about constructing one of the best ICs, not preventing to debug advert hoc Perl scripts.
One other disadvantage is the query of robustness of the parsing functionality for SystemVerilog, VHDL or UPF. To achieve success, the platform have to be primarily based on a broadly used and examined HDL parser library. With out it, every new design or venture will reveal extra limitations of the parser. Solely parsers actively utilized by 1000’s of engineers and actively maintained can deal with arbitrary new designs.
Closing gaps in a CAD movement and getting off the infinite cycle of script design and debug, a licensed CAD software improvement platform supplies the aptitude to leverage commercial-grade HDL parsers whereas simplifying their use.
Daniel Hoggar is a senior member of technical workers at Verific Design Automation.
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