APPLY HERE ON LINKEDIN
Location: Bangalore, Noida and Coimbatore
Firm: Apex Semiconductor
You’ll personal the block and chip stage STA evaluation and methodology for top efficiency and low energy designs in addition to advanced SOCs.
Obligations
- Block stage and chip stage timing evaluation.
- Timing evaluation of various sorts of interfaces at chip stage.
- Work with the design and implementation groups to develop and qualify timing constraints.
- Work on methodology growth for timing evaluation and timing closure.
- Contribute to the STA move growth.
- Work intently with the bodily design engineers to resolve implementation associated timing points.
- Create methodologies for personalized timing checks for various IPs, interfaces and so on.
- Validation of library timing information (qualification of libraries).
Necessities
- BTech/MTech from a reputed college.
- 2-4 years of hands-on expertise in timing evaluation.
- Expertise in doing SoC stage timing evaluation.
- Must be conversant in timing evaluation for hierarchical designs.
- Familiarity with various kinds of interfaces like PCIe, SATA, USB, DDR and so on.
- Labored on know-how nodes 16nm and 7nm.
- Proficiency in trade commonplace STA instruments (Tempus and PrimeTime).
- Good scripting talent in Tcl and Python.
- Familiarity with totally different bodily design instruments ideally Cadence Innovus.
