It’s Not An APU, It’s What Occurs When Ponte Vecchio Meets Sapphire Rapids
Intel has some severe HPC plans for the long run, combining x86 CPU cores and Xe GPU cores right into a single bundle of your alternative known as an XPU. Rialto Bridge merchandise will ship in a big array of packages, some with x86 CPU cores and Xe cores, whereas others may be strictly x86 cores or Xe cores, which you’ll select to greatest meet your processing wants. The efficiency enhancements they’re suggesting it will convey are spectacular; suggesting you must anticipate 5 instances the efficiency per watt, reminiscence capability, and reminiscence bandwidth in comparison with the competitors. That’s one thing NVIDIA is unlikely to take mendacity down.
Intel additionally talked up Ponte Vecchio on the Worldwide Supercomputing Convention in Hamburg, Germany as we nonetheless haven’t really seen it within the wild. We are going to quickly have extra particulars as a number of Intel based mostly supercomputers needs to be booted up quickly, together with the Aurora supercomputer at Argonne Nationwide Laboratory, amongst others.
We all know Ponte Vecchio will make use of HBM2e reminiscence, which suggests the existence of HBM3 being utilized in Rialto Bridge to account for the elevated reminiscence bandwidth. The brand new XPU will probably additionally make use of PCIe 5.0 and 6.0 to make sure it’s pipes are thick sufficient to deal with all this elevated bandwidth. Pop by The Register, or look beneath for a hyperlink to Serve The House’s protection in case you are interested by the way forward for Intel’s excessive powered silicon, together with this new Falcon Shores XPU design.
