2x Density Scaling, 20% Improved Efficiency

Going down this week is the IEEE’s annual VLSI Symposium, one of many business’s main occasions for disclosing and discussing new chip manufacturing strategies. One of the anticipated displays scheduled this 12 months is from Intel, who’s on the present to stipulate the bodily and efficiency traits of their upcoming Intel 4 course of, which shall be used for merchandise set to be launched in 2023. The event of the Intel 4 course of represents a essential milestone for Intel, because it’s the primary Intel course of to include EUV, and it’s the primary course of to maneuver previous their troubled 10nm node – making it Intel’s first likelihood to get again on monitor to re-attaining fab supremacy.

Intel’s scheduled to ship their Intel 4 presentation on Tuesday, in a chat/paper entitled “Intel 4 CMOS Expertise That includes Superior FinFET Transistors optimized for Excessive Density and Excessive-Efficiency Computing”. However this morning, forward of the present, they re publishing the paper and all of its related figures, giving us our first take a look at what sort of geometries Intel is attaining, in addition to some extra details about the supplies getting used.

Beforehand often known as Intel’s 7nm course of, Intel 4 is Intel’s first time utilizing EUV lithography for his or her chips. A very long time coming, using EUV guarantees each to permit Intel to attract the form of ever-smaller options wanted for extra superior manufacturing nodes, whereas on the similar time letting Intel reduce down on the variety of manufacturing steps required through at present’s multi-patterning DUV strategies. Unusually, Intel finds itself as the ultimate of the large three fabs to faucet into EUV – the corporate handed on EUV for the 10nm era as they didn’t really feel it was prepared, after which delays with 10nm and 7nm pushed again Intel’s EUV adoption level considerably.  Consequently, Intel will get to spring ahead on the premise of EUV-driven positive factors, although they are going to nonetheless should make up for misplaced time and TSMC’s expertise benefit.

The event of Intel 4 can be a essential juncture for the corporate, because it lastly permits them to maneuver previous their troubled 10nm course of. Whereas Intel has managed to make one thing appropriate of their 10nm course of nodes – particularly with their most up-to-date 10nm Enhanced SuperFin variant, which we higher know as Intel 7 – it’s not been with out totally an excessive amount of blood, sweat, and years. Intel believes they tried to do an excessive amount of abruptly with 10nm – each with reference to scaling and in too many new manufacturing strategies – which in flip set them again years as they untangled that mess to search out and iterate on what went improper. Unsurprisingly then, Intel is being a bit much less aggressive with their first EUV node, and the corporate general has taken a way more modular growth method going ahead, permitting for brand new applied sciences to be applied (and, if needed, debugged) in steps.

Intel 4, in flip, shall be first used for Intel’s forthcoming Meteor Lake shopper SoC, which is anticipated to be the premise of Intel’s 14^th era Core processor household. Although not transport till 2023, Intel already has Meteor Lake up and operating of their labs, as per the corporate’s typical bring-up course of. Together with brining a big bump in course of applied sciences, Meteor Lake can even be Intel’s first tiled/chiplet-based shopper CPU, utilizing a mixture of tiles for I/O, CPU cores, and GPU cores.

Intel 4 Bodily Parameters: 2x Density Over Intel 7, Cobalt Use Continues

Diving into the Intel 4 course of, Intel has got down to sort out just a few various things right here. Before everything is, in fact, density. Intel is striving to maintain Moore’s Legislation alive, and whereas the coinciding demise of Dennard scaling signifies that it’s now not a easy matter of lighting up twice as many transistors on each era, the next transistor density affords smaller chips at with the identical {hardware}, or throwing in additional cores (or different processing {hardware}) with newer desgins.

Of the figures Intel is releasing on this week’s paper, the fin pitch on Intel 4 is right down to 30nm, 0.88x the scale of Intel 7’s 34nm pitch. Equally, the pitch between contact gates is now 50nm, down from 60nm earlier than. However most importantly, the minimal metallic pitch for the bottom layer (M0) can be 30nm, 0.75x the scale of the M0 pitch on Intel 7.

Intel’s library peak has additionally been reduce down as nicely. The cell peak for the high-performance library on Intel 4 is 240nm, which is barely 0.59 x the peak of an HP cell on Intel 7.

Consequently, Intel is claiming a 2x enhance in density for Intel 4 versus Intel 7 – or extra particularly, a halving of measurement for transistors – a conventional, full node’s enchancment in transistor density.

Since chips are 2D constructs, the metric Intel makes use of for that is multiplying the HP cell peak by the contacted poly pitch, which is basically the width of a cell. In that case they get 24,408 nm² for Intel 7, and a flat 12,000 nm² for Intel 4, 0.49x the world of the Intel 7-based cell.

In fact, not each sort of construction scales by the identical issue with a brand new course of node, and Intel 4 is not any totally different. In line with the corporate SRAM cells on Intel 4 are solely round 0.77x the scale of the identical cells on Intel 7. So whereas standardized logic cells have doubled in density, SRAM density (for equal SRAM sorts) has solely improved by 30% or so.

And, sadly, whereas Intel is speaking about density with respect to straightforward cells, they aren’t formally disclosing precise transistor density figures. For now, what Intel is telling us is that the general transistor density interprets nicely with the 2x determine they’re at present offering. Which, primarily based on what we learn about Intel 7 and its 80 million transistors per mm² density for HP libraries, would place Intel 4’s HP libraries at round 160MTr/mm².

Since these figures are for Intel’s decrease density high-performance libraries, the apparent follow-up query to that might be what the figures are for prime density libraries – which historically squeeze issues much more in trade for decreased clockspeeds. Nonetheless because it seems, Intel gained’t be growing excessive density libraries for Intel 4. As a substitute, Intel 4 shall be a pure high-performance node, and high-density designs will include the successive node, Intel 3.

This uncommon growth comes because of Intel’s modularization efforts for course of node growth. Intel has basically adopted a tick tock-like technique for node growth over the following half decade or so, with Intel growing an preliminary node primarily based on a brand new know-how (e.g. EUV or Excessive-NA machines), after which following that up with a extra refined/optimized successor. Within the case of Intel 4, whereas it’s doing essential pioneering work for EUV inside Intel’s fabs, the corporate’s greater plans are for Intel 3 to be their long-term, long-lived EUV node.

All of which signifies that Intel has no want for high-density libraries with Intel 4, since it’s slated to get replaced with the extra fully-featured Intel 3 inside a 12 months or so. And since Intel 3 is design appropriate with Intel 4, it’s clear to see how Intel is pushing its personal design groups to make use of the latter course of every time timetables permit. Intel Foundry Providers prospects can even be a in an analogous boat – they can use Intel 4, however IFS is extra targeted on supplying entry to and design assist with Intel 3.

Getting again to Intel 4 itself, the brand new node comes with a big change to the metallic layers as in comparison with Intel’s 10nm processes. Intel famously changed copper with cobalt on the lowest layers of its 10nm course of, one thing that the corporate deemed needed for transistor longevity (electromigration resistance) causes. Sadly, cobalt isn’t pretty much as good from a efficiency (clockspeed) perspective, and it’s lengthy been suspected that the swap to cobalt was one of many main hindrances in 10nm growth for Intel.

For Intel 4, in flip, Intel is taking half a step again. The corporate continues to be utilizing cobalt of their processes, however now moderately than pure cobalt they’re utilizing what they’re calling Enhanced Copper (eCu), which is copper cladded with cobalt. The thought behind eCu is to have the most effective of each phrases, sustaining the efficiency of a doped copper metallization layer, whereas nonetheless getting the electromigration resistance advantages of cobalt.

Electromigration lifetimes and line Resistance are in contrast for various metallurgy choices.

And whereas Intel is now not utilizing pure cobalt, in some respects their use of cobalt is rising general. Whereas Intel’s 10nm processes solely used cobalt for the contact gate and first two metallic layers, Intel 4 is increasing using eCu to the primary 5 metallic layers. Consequently, the lowest-third of the whole metallic layer stack in a chip is utilizing Intel’s cobalt-clad copper. Intel has, nonetheless, eliminated cobalt from the gate itself; that’s now pure tungsten, moderately than a mixture of tungsten and cobalt.

All instructed, the variety of metallic layers for Intel 4 has elevated versus Intel 7. Whereas the latter had 15 metallic layers for logic, Intel 4 squeezes in a 16^th layer. That is joined by the same old two layers for energy routing, which Intel phrases its large layers on account of their comparatively huge pitches of 1080nm and 4000nm.

Alongside the tighter gate and metallic layer pitches, one other space the place Intel is gaining density enhancements from design rule modifications for interconnects. With Intel 4, Intel has moved to what they’re calling a gridded interconnect design, which briefly, solely permits for vias going between metallic layers to be positioned per a pre-determined grid. Beforehand, vias might be positioned anyplace, which allowed for some flexibility, however had different trade-offs.

Design guidelines modified from conventional (left) to gridded (proper) to enhance yield and enhance efficiency although capacitance discount

In line with Intel, using grids has improved each the yields of the method by lowering variability, in addition to how they go about optimizing designs. The swap additionally has a aspect advantage of permitting Intel to keep away from having to make use of complicated, multi-patterned EUV for his or her interconnects.

Lastly, as beforehand talked about, using EUV can be permitting Intel to cut back the variety of steps (and the variety of masks) required to fab a chip. Whereas the corporate isn’t providing absolute numbers, on a relative foundation Intel 4 requires 20% fewer masks than Intel 7. Had Intel not achieved this, the variety of masks required would have as an alternative shot up by round 30% as a result of variety of multi-patterning steps required.

In depth employment of EUV allows function scaling and course of simplification

Using EUV can be having a constructive influence on Intel’s yields. Although the corporate isn’t offering precise numbers, the discount within the variety of steps gives fewer alternatives for something to go improper that might introduce a defect on a wafer.

Intel 4 Efficiency: 21.5% Extra Perf at iso-power/40% Much less Energy at iso-frequency

Density enhancements apart, what sort of efficiency enhancements is Intel seeing for the Intel 4 course of? Briefly, Intel is seeing above-average positive factors in each frequencies and energy effectivity.

Circuit evaluation of business commonplace core exhibits 21.5% efficiency achieve at matched energy over Intel 7 at 0.65V. 8VT circulate allows 5% efficiency achieve over 6VT at excessive voltages.

At an iso-power of 0.65v, Intel is seeing a 21.5% enhance in clockspeeds attainable versus Intel 7. With that stated, 0.65v is on the low finish of the curve, and Intel’s graph does present diminishing returns as you go farther up in voltage; at 0.85v and past the iso-power positive factors are nearer to 10%. In line with Intel, they’ll squeeze out one other 5% or so through the use of cells designed for larger threshold voltages (8VT), which comes at a value of upper whole energy consumption versus commonplace cells.

And if we take issues from the opposite finish, Intel is reporting even bigger positive factors on the ability effectivity entrance with Intel 4. At iso-frequency – on this case round 2.1GHz – Intel is seeing 40% decrease energy consumption. There are once more diminishing returns as frequencies enhance (up till Intel 7 hits its sensible limits), nevertheless it’s extra constant than the efficiency/frequency positive factors. This mirrors what we’ve seen with different course of nodes – together with Intel 7 at its launch – the place newer nodes are lowering energy consumption at a a lot better fee than they’re enabling larger clockspeeds. A full CPU constructed on the Intel 4 course of might conceivably save an excessive amount of energy – as long as you don’t thoughts it not clocking any larger than earlier than.

All instructed, the efficiency positive factors outlined in Intel’s paper mirror those who they’ve been claiming up till now, such because the 20% perf-per-watt positive factors for Intel 4 mentioned finally summer time’s course of roadmap replace. For the final 12 months Intel has been approaching the ending line for Intel 4 growth, in order their paper outlines, they look like on-track for delivering on their efficiency positive factors.

In the meantime, Intel can be reporting good developments in price scaling from Intel 7 to Intel 4, although as soon as once more the corporate isn’t offering particular numbers. 1 EUV layer does find yourself being costlier than 1 DUV layer, however as a result of EUV eliminates a bunch of multi-patterning, it helps to carry down the overall prices by lowering the overall variety of steps. The swap to EUV can be lowering a little bit of the capital stress on Intel, as Intel 4 doesn’t require fairly as a lot clear room area (although it’s under no circumstances a small quantity general).

In the end, as Intel appears to be like to ship Meteor Lake and different first-generation Intel 4 merchandise in 2023, what stays to be seen is how rapidly Intel can get their new course of node up and operating to the requirements of high-volume manufacturing. With Meteor Lake samples already in Intel’s labs, Intel is getting ever nearer to lastly coming into the EUV age. However for Intel, hitting all of their targets getting there means not simply scaling up manufacturing from their Hillsboro growth fab, but additionally mastering the fascinating job of replicating their course of to Eire and the opposite Intel fabs that shall be used for Intel 4.